`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/01/10 20:32:21
// Design Name: 
// Module Name: led_stream
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module led_stream(
    output reg[3:0] led, // led4-1
    input   clk,
    input   rst_n
);
reg[31:0] cnt;
reg[1:0] led_on_number;

parameter CLOCK_FREQ = 50000000;
parameter COUNTER_MAX_CNT = CLOCK_FREQ/2 - 1;

always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        cnt <= 32'd0;
        led_on_number <= 2'd0;
    end
    else begin
        cnt <= cnt+1'b1;
        if(cnt == COUNTER_MAX_CNT) begin
            cnt <= 32'd0;
            led_on_number <= led_on_number+1'b1;
        end
    end
end

always@(led_on_number)begin
    case(led_on_number)
        0: led<=4'b0001;
        1: led<=4'b0010;
        2: led<=4'b0100;
        3: led<=4'b1000;
    endcase
end


endmodule
